• JEDEC JESD 78C

JEDEC JESD 78C

  • IC LATCH-UP TEST
  • standard by JEDEC Solid State Technology Association, 09/01/2010
  • Category: JEDEC

$72.00 $36.00

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD82-9B

JEDEC JESD82-9B

DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS..

$34.00 $67.00

JEDEC J-STD-609

JEDEC J-STD-609

MARKING AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUT..

$30.00 $59.00

JEDEC JESD82-16A

JEDEC JESD82-16A

DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM AP..

$40.00 $80.00

JEDEC JESD82-19A

JEDEC JESD82-19A

DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIM..

$36.00 $72.00