• JEDEC JESD 78B

JEDEC JESD 78B

  • IC LATCH-UP TEST
  • standard by JEDEC Solid State Technology Association, 12/01/2008
  • Category: JEDEC

$72.00 $36.00

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a device's latch-up capability so that both the user and supplier understand a device's latch-up capabilities. It is applicable to NMOS, CMOS, Bipolar, and all variations and combinations of these technologies. Latch-up is an extremely important factor in determining product reliability. This document contains the corrected figure 4 to include T6 on page 12, this change was made in January 1998.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD20

JEDEC JESD20

STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES..

$96.00 $191.00

JEDEC JESD 24-4 (R2002)

JEDEC JESD 24-4 (R2002)

ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTE..

$28.00 $56.00

JEDEC JESD 24-3

JEDEC JESD 24-3

ADDENDUM No. 3 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-D..

$30.00 $59.00

JEDEC JESD 24-2 (R2002)

JEDEC JESD 24-2 (R2002)

ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD..

$27.00 $53.00