• JEDEC JESD 22-A117B

JEDEC JESD 22-A117B

  • ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
  • standard by JEDEC Solid State Technology Association, 03/01/2009
  • Category: JEDEC

$62.00 $31.00

This method establishes a standard procedure for determining the data cycling endurance and data retention capability of non-volatile memory cells. It is intended as a qualification and monitor test procedure. This test is also applicable to FLASH EEPROM integrated circuits and Erasable Programmable Logic Devices (EPLD) with embedded EEPROM or FLASH memory.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD 12-1B

JEDEC JESD 12-1B

ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS..

$30.00 $60.00

JEDEC JESD 27

JEDEC JESD 27

CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES..

$44.00 $87.00

JEDEC JESD8-4

JEDEC JESD8-4

ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STAN..

$24.00 $48.00

JEDEC JESD3-C

JEDEC JESD3-C

STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMM..

$39.00 $78.00