JEDEC JEP150.01
- STRESS-TEST-DRIVEN QUALIFICATION OF AND FAILURE MECHANISMS ASSOCIATED WITH ASSEMBLED SOLID STATE SURFACE-MOUNT COMPONENTS
- standard by JEDEC Solid State Technology Association, 06/01/2013
- Category: JEDEC
$67.00
$34.00
This publication contains a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products, in particular leadless chip carriers, ball grid array (BGA) packages, direct chip attach die and packages with exposed pads that are attached to the PWB for thermal considerations. Assembly level testing may not be a prerequisite for device qualification; however, if the effect of assembly conditions on the component is not known, there could be reliability concerns for that component that are not evident in component level testing. As such, it is recommended that assembly level testing be performed to determine if there are any adverse effects on that component due to its assembly to a PWB.
PDF
All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.
Multi-User Access
After purchasing, you have the ability to assign each license to a specific user.
Printable
At any time, you are permitted to make printed copies for your and your members' reference use.
