IEEE 1076.6-2004
- IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
- standard by IEEE, 10/11/2004
- Category: IEEE
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Revision Standard - Inactive-Withdrawn.This document specifies a standard for use of very high-speed integrated circuit hardwaredescription language (VHDL) to model synthesizable register-transfer level digital logic. Astandard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset ofthe VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructsare identified that should be ignored or flagged as errors.
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